[M-Labs devel] lm32 status JTAG/debug interface

[Christian Wick]

Hello,

what is the status of the lm32 JTAG/debug interface in the current code
that is available on github?

I know that there is a JTAG tap for the Spartan6, but how can it be used
for gdb debugging?
I have found some info from Michael Walle on the web who has started to
implement lm32 support into openocd and who also implemented the
Spartan6 tap.
So I guess that the plan was/is to use a Xilinx cable to connect to the
FPGA JTAG port using openocd and then use gdb for debugging, right?

I have also found two discussions about a generic tap controller for the
lm32:
http://www.mikrocontroller.net/topic/341852#3793537
http://www.mikrocontroller.net/topic/333293#3793536

From these dicussions I got the info that there are some unknown things
concerning the JTAG implementation (ER1, ER2 and jtagconn16).
However, since the complete code of the lm32 is available and openocd is
also open source, the implmentation of the a generic tap controller on
normal FPGA I/Os pins using openocd should be possible, right?

Best regards,
Christian

[Sébastien Bourdeauducq]

Hi,

what we've used instead of the JTAG is the serial port. Entering the
debugger is done by sending a break character (asserting the line for
longer than a character, without a stop bit) which causes a hardware
jump to a debug ROM that handles the communications, reads/writes
registers and memory, sets breakpoints/watchpoints, etc.

You may find the code in the 'milkymist' repository - it's not ported to
misoc yet, but should.

Sébastien

[Christian Wick]

Post by Sébastien Bourdeauducq
Hi,
what we've used instead of the JTAG is the serial port. Entering the
debugger is done by sending a break character (asserting the line for
longer than a character, without a stop bit) which causes a hardware
jump to a debug ROM that handles the communications, reads/writes
registers and memory, sets breakpoints/watchpoints, etc.
You may find the code in the 'milkymist' repository - it's not ported to
misoc yet, but should.
Sébastien

Thanks for the hint.
I wonder if the generic tap controller would be possible though.
Is there anything that speaks against it? For example is there something
missing in the lm32 core code for proper single stepping?

I have found this code here:
http://git.serverraum.org/?p=mw/openocd-lm32.git;a=blob;f=src/target/lm32.c;hb=HEAD

This code seems to access the lm32 by using the JTAG interface.
However, the code does not implement single stepping.
I wonder which version of the lm32 code (especially the jtag tap code)
was used to get openocd working.

What would I like to do?
I want to use my FT2232H based JTAG adapter (Olimex ARM-USB-TINY-H) to
connect to some generic I/O pins of the FPGA which are connected to the
lm32 core for JTAG debugging using openocd and lm32-elf-gdb.

Currently it seems that most things are there, but not all.

BR,
Christian

[Sébastien Bourdeauducq]

Post by Christian Wick
I wonder if the generic tap controller would be possible though.
Is there anything that speaks against it?

No, except for the inconvenience of having to connect two JTAG cables
(one for the bitstream and the other one for the CPU), and the fact that
JTAG uses too many IO pins (only 2 are sufficient for this purpose).

Post by Christian Wick
For example is there something
missing in the lm32 core code for proper single stepping?

Single stepping works fine with the serial interface, so no.

Post by Christian Wick
This code seems to access the lm32 by using the JTAG interface.
However, the code does not implement single stepping.
I wonder which version of the lm32 code (especially the jtag tap code)
was used to get openocd working.

AFAIK we never fully got OpenOCD to work.

Post by Christian Wick
What would I like to do?
I want to use my FT2232H based JTAG adapter (Olimex ARM-USB-TINY-H) to
connect to some generic I/O pins of the FPGA which are connected to the
lm32 core for JTAG debugging using openocd and lm32-elf-gdb.
Currently it seems that most things are there, but not all.

Maybe you can also reconfigure the FT2232H as UART and use the existing
code. Note that the new UART design in MiSoC can reach high speeds - we
tested it to 3Mbps. The FT2232H should at least support that speed too.

Sébastien

[Christian Wick]

Post by Sébastien Bourdeauducq

Post by Christian Wick
This code seems to access the lm32 by using the JTAG interface.
However, the code does not implement single stepping.
I wonder which version of the lm32 code (especially the jtag tap code)
was used to get openocd working.

AFAIK we never fully got OpenOCD to work.

Was the openocd lm32 target supposed to work with the Spartan6 JTAG tap
using one of the USER instructions in the IR?

Post by Sébastien Bourdeauducq

Post by Christian Wick
What would I like to do?
I want to use my FT2232H based JTAG adapter (Olimex ARM-USB-TINY-H) to
connect to some generic I/O pins of the FPGA which are connected to the
lm32 core for JTAG debugging using openocd and lm32-elf-gdb.
Currently it seems that most things are there, but not all.

Maybe you can also reconfigure the FT2232H as UART and use the existing
code. Note that the new UART design in MiSoC can reach high speeds - we
tested it to 3Mbps. The FT2232H should at least support that speed too.

Interesting. I will look into this. I saw that you realized this by
using a gdb stub which is the monitor code running on the lm32.
You are using the external break signal from the UART module to trap
into this gdb stub, correct?
Then the lm32-elf-gdb could be used to connect to the device
/dev/ttyUSB0 for example and start debugging.

I think a general tap could be easily added by using this general tap
and remove the additional scan chains (Mbist, Boundary):
http://opencores.org/websvn,filedetails?repname=jtag&path=%2Fjtag%2Ftrunk%2Ftap%2Frtl%2Fverilog%2Ftap_top.v
It basically offers the same functionalty as the module BSCAN_SPARTAN6
does for example. It also offers the select signal "debug_select_o" and
exposes the signals "shift_dr_o" and "update_dr_o"
to expose the state signal. However, it is a fully compilant generic
JTAG TAP.

BR,
Christian

[Sébastien Bourdeauducq]

Post by Christian Wick
Interesting. I will look into this. I saw that you realized this by
using a gdb stub which is the monitor code running on the lm32.
You are using the external break signal from the UART module to trap
into this gdb stub, correct?
Then the lm32-elf-gdb could be used to connect to the device
/dev/ttyUSB0 for example and start debugging.

Yes:
http://m-labs.hk/milkymist-wiki/wiki/index.php%3Ftitle=Using_GDB_in-system_debugger.html

Post by Christian Wick
I think a general tap could be easily added by using this general tap
http://opencores.org/websvn,filedetails?repname=jtag&path=%2Fjtag%2Ftrunk%2Ftap%2Frtl%2Fverilog%2Ftap_top.v

Yes, but why bother? It's not better than the UART method and it's more
complicated.

Sébastien

[Michael Walle]

Post by Christian Wick

Post by Sébastien Bourdeauducq

Post by Christian Wick
This code seems to access the lm32 by using the JTAG interface.
However, the code does not implement single stepping.
I wonder which version of the lm32 code (especially the jtag tap code)
was used to get openocd working.

AFAIK we never fully got OpenOCD to work.

Was the openocd lm32 target supposed to work with the Spartan6 JTAG tap
using one of the USER instructions in the IR?

Yes

-michael

[Michael Walle]

Post by Christian Wick

Post by Sébastien Bourdeauducq
Hi,
what we've used instead of the JTAG is the serial port. Entering the
debugger is done by sending a break character (asserting the line for
longer than a character, without a stop bit) which causes a hardware
jump to a debug ROM that handles the communications, reads/writes
registers and memory, sets breakpoints/watchpoints, etc.
You may find the code in the 'milkymist' repository - it's not ported to
misoc yet, but should.
Sébastien

Thanks for the hint.
I wonder if the generic tap controller would be possible though.
Is there anything that speaks against it? For example is there something
missing in the lm32 core code for proper single stepping?
http://git.serverraum.org/?p=mw/openocd-lm32.git;a=blob;f=src/target/lm32.c;
hb=HEAD

LM32 with jtag and OpenOCD (connected to the native xilinx jtag and using the
bscan primitive) was very slow.

-michael

[Yann Sionneau]

Post by Christian Wick
Hello,
what is the status of the lm32 JTAG/debug interface in the current code that is available on github?
I know that there is a JTAG tap for the Spartan6, but how can it be used for gdb debugging?
I have found some info from Michael Walle on the web who has started to implement lm32 support into openocd and who also implemented the Spartan6 tap.
So I guess that the plan was/is to use a Xilinx cable to connect to the FPGA JTAG port using openocd and then use gdb for debugging, right?
http://www.mikrocontroller.net/topic/341852#3793537
http://www.mikrocontroller.net/topic/333293#3793536
From these dicussions I got the info that there are some unknown things concerning the JTAG implementation (ER1, ER2 and jtagconn16).
However, since the complete code of the lm32 is available and openocd is also open source, the implmentation of the a generic tap controller on normal FPGA I/Os pins using openocd should be possible, right?
Best regards,

If regardless of what Sebastien told you about the uart debugging via the GDB stub monitor you still want to go the openocd+jtag way, you can contact Drasko Draskovic and ask him about his openocd+lm32 work.

He had it to work at some point. But as far as I know he never released his work.

You can contact him at : drasko [dot] draskovic [at] gmail [dot] com

Cheers!