Discussion:
[M-Labs devel] [PATCH 4/5] fhdl.structure: remove unused imports
Robert Jordens
2014-08-17 20:56:32 UTC
Permalink
---
migen/fhdl/structure.py | 2 --
1 file changed, 2 deletions(-)

diff --git a/migen/fhdl/structure.py b/migen/fhdl/structure.py
index ba84dd8..4525266 100644
--- a/migen/fhdl/structure.py
+++ b/migen/fhdl/structure.py
@@ -1,5 +1,3 @@
-import inspect
-import re
import builtins
from collections import defaultdict
--
1.9.1
Robert Jordens
2014-08-17 20:56:33 UTC
Permalink
---
migen/fhdl/structure.py | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/migen/fhdl/structure.py b/migen/fhdl/structure.py
index 4525266..5b6cc28 100644
--- a/migen/fhdl/structure.py
+++ b/migen/fhdl/structure.py
@@ -511,8 +511,10 @@ class ClockDomain:
self.name = tracer.get_obj_var_name(name)
if self.name is None:
raise ValueError("Cannot extract clock domain name from code, need to specify.")
- if len(self.name) > 3 and self.name[:3] == "cd_":
+ if self.name.startswith("cd_"):
self.name = self.name[3:]
+ if self.name[0].isdigit():
+ raise ValueError("Clock domain name can not start with a number.")
self.clk = Signal(name_override=self.name + "_clk")
if reset_less:
self.rst = None
--
1.9.1
Robert Jordens
2014-08-17 20:56:30 UTC
Permalink
---
migen/fhdl/structure.py | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/migen/fhdl/structure.py b/migen/fhdl/structure.py
index aa33888..3edc286 100644
--- a/migen/fhdl/structure.py
+++ b/migen/fhdl/structure.py
@@ -275,7 +275,7 @@ class Signal(Value):
return "<Signal " + (self.backtrace[-1][0] or "anonymous") + " at " + hex(id(self)) + ">"

@classmethod
- def like(cls, other):
+ def like(cls, other, **kwargs):
"""Create Signal based on another.

Parameters
@@ -286,7 +286,7 @@ class Signal(Value):
See `migen.fhdl.bitcontainer.value_bits_sign`() for details.
"""
from migen.fhdl.bitcontainer import value_bits_sign
- return cls(value_bits_sign(other))
+ return cls(bits_sign=value_bits_sign(other), **kwargs)

class ClockSignal(Value):
"""Clock signal for a given clock domain
--
1.9.1
Robert Jordens
2014-08-17 20:56:31 UTC
Permalink
---
migen/fhdl/structure.py | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/migen/fhdl/structure.py b/migen/fhdl/structure.py
index 3edc286..ba84dd8 100644
--- a/migen/fhdl/structure.py
+++ b/migen/fhdl/structure.py
@@ -81,17 +81,20 @@ class Value(HUID):
def __getitem__(self, key):
from migen.fhdl.bitcontainer import flen

+ n = flen(self)
if isinstance(key, int):
+ if key >= n:
+ raise IndexError
if key < 0:
- key += flen(self)
+ key += n
return _Slice(self, key, key+1)
elif isinstance(key, slice):
- start, stop, step = key.indices(flen(self))
+ start, stop, step = key.indices(n)
if step != 1:
return Cat(self[i] for i in range(start, stop, step))
return _Slice(self, start, stop)
else:
- raise KeyError
+ raise TypeError

def eq(self, r):
"""Assignment
--
1.9.1
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